torchlogix.CompiledLogicNet

class torchlogix.CompiledLogicNet(model, input_shape, device='cpu', num_bits=64, cpu_compiler='gcc', verbose=False, use_bitpacking=True, apply_groupsum_scaling=True)

Unified compiled logic network that handles convolutional, pooling, and linear layers.

__init__(model, input_shape, device='cpu', num_bits=64, cpu_compiler='gcc', verbose=False, use_bitpacking=True, apply_groupsum_scaling=True)

Initialize internal Module state, shared by both nn.Module and ScriptModule.

Methods

__init__(model, input_shape[, device, ...])	Initialize internal Module state, shared by both nn.Module and ScriptModule.
add_module(name, module)	Add a child module to the current module.
apply(fn)	Apply fn recursively to every submodule (as returned by .children()) as well as self.
bfloat16()	Casts all floating point parameters and buffers to bfloat16 datatype.
buffers([recurse])	Return an iterator over module buffers.
children()	Return an iterator over immediate children modules.
compile([opt_level, save_lib_path, verbose])	Compile the network to a shared library.
cpu()	Move all model parameters and buffers to the CPU.
cuda([device])	Move all model parameters and buffers to the GPU.
double()	Casts all floating point parameters and buffers to double datatype.
eval()	Set the module in evaluation mode.
export_hdl(output_dir[, module_name, ...])	Export the network as HDL files.
extra_repr()	Return the extra representation of the module.
float()	Casts all floating point parameters and buffers to float datatype.
forward(x[, verbose])	Forward pass through the compiled network.
get_buffer(target)	Return the buffer given by target if it exists, otherwise throw an error.
get_c_code()	Generate the complete C code for the network.
get_extra_state()	Return any extra state to include in the module's state_dict.
get_gate_code(var1, var2, gate_op)	Generate C code for a logic gate operation.
get_gate_verilog(var1, var2, gate_op)	Generate Verilog code for a logic gate operation.
get_parameter(target)	Return the parameter given by target if it exists, otherwise throw an error.
get_submodule(target)	Return the submodule given by target if it exists, otherwise throw an error.
get_verilog_code([module_name, pipeline_stages])	Generate complete Verilog code for the network.
half()	Casts all floating point parameters and buffers to half datatype.
ipu([device])	Move all model parameters and buffers to the IPU.
load(save_lib_path, input_shape[, ...])	Load a compiled network from a shared library.
load_state_dict(state_dict[, strict, assign])	Copy parameters and buffers from state_dict into this module and its descendants.
modules()	Return an iterator over all modules in the network.
mtia([device])	Move all model parameters and buffers to the MTIA.
named_buffers([prefix, recurse, ...])	Return an iterator over module buffers, yielding both the name of the buffer as well as the buffer itself.
named_children()	Return an iterator over immediate children modules, yielding both the name of the module as well as the module itself.
named_modules([memo, prefix, remove_duplicate])	Return an iterator over all modules in the network, yielding both the name of the module as well as the module itself.
named_parameters([prefix, recurse, ...])	Return an iterator over module parameters, yielding both the name of the parameter as well as the parameter itself.
parameters([recurse])	Return an iterator over module parameters.
register_backward_hook(hook)	Register a backward hook on the module.
register_buffer(name, tensor[, persistent])	Add a buffer to the module.
register_forward_hook(hook, *[, prepend, ...])	Register a forward hook on the module.
register_forward_pre_hook(hook, *[, ...])	Register a forward pre-hook on the module.
register_full_backward_hook(hook[, prepend])	Register a backward hook on the module.
register_full_backward_pre_hook(hook[, prepend])	Register a backward pre-hook on the module.
register_load_state_dict_post_hook(hook)	Register a post-hook to be run after module's load_state_dict() is called.
register_load_state_dict_pre_hook(hook)	Register a pre-hook to be run before module's load_state_dict() is called.
register_module(name, module)	Alias for add_module().
register_parameter(name, param)	Add a parameter to the module.
register_state_dict_post_hook(hook)	Register a post-hook for the state_dict() method.
register_state_dict_pre_hook(hook)	Register a pre-hook for the state_dict() method.
requires_grad_([requires_grad])	Change if autograd should record operations on parameters in this module.
set_extra_state(state)	Set extra state contained in the loaded state_dict.
set_submodule(target, module[, strict])	Set the submodule given by target if it exists, otherwise throw an error.
share_memory()	See torch.Tensor.share_memory_().
state_dict(*args[, destination, prefix, ...])	Return a dictionary containing references to the whole state of the module.
to(*args, **kwargs)	Move and/or cast the parameters and buffers.
to_empty(*, device[, recurse])	Move the parameters and buffers to the specified device without copying storage.
train([mode])	Set the module in training mode.
type(dst_type)	Casts all parameters and buffers to dst_type.
xpu([device])	Move all model parameters and buffers to the XPU.
zero_grad([set_to_none])	Reset gradients of all model parameters.

Attributes

T_destination
call_super_init
dump_patches
training

__init__(model, input_shape, device='cpu', num_bits=64, cpu_compiler='gcc', verbose=False, use_bitpacking=True, apply_groupsum_scaling=True)

Initialize internal Module state, shared by both nn.Module and ScriptModule.

get_gate_code(var1, var2, gate_op)

Generate C code for a logic gate operation.

Return type:

str

get_gate_verilog(var1, var2, gate_op)

Generate Verilog code for a logic gate operation.

Parameters:

• var1 (str) – Name of first input variable (Verilog syntax)

• var2 (str) – Name of second input variable (Verilog syntax)

• gate_op (int) – Gate operation ID (0-15)

Return type:

str

Returns:

Verilog expression string

get_c_code()

Generate the complete C code for the network.

Return type:

str

get_verilog_code(module_name='torchlogix_net', pipeline_stages=0)

Generate complete Verilog code for the network.

Parameters:

• module_name (str) – Name of the top-level Verilog module

• pipeline_stages (int) – Number of pipeline stages to insert (0 = fully combinational) - 0: Fully combinational (no registers, 1 cycle latency, may not synthesize for large models) - 1: Single output register (1 cycle latency, helps synthesis) - N: Divide layers into N pipeline stages (N cycle latency) - Use len(layers) for full layer-level pipelining

Return type:

str

Returns:

Complete Verilog code as a string with specified pipelining

Examples

# Fully combinational (original behavior) verilog = model.get_verilog_code(pipeline_stages=0)

# Output register only (helps with large designs) verilog = model.get_verilog_code(pipeline_stages=1)

# 4 pipeline stages (divide layers into 4 groups) verilog = model.get_verilog_code(pipeline_stages=4)

# Full layer-level pipelining (register between each layer) verilog = model.get_verilog_code(pipeline_stages=999) # or len(layers)

export_hdl(output_dir, module_name='torchlogix_net', format='verilog', pipeline_stages=0)

Export the network as HDL files.

Parameters:

• output_dir (str) – Directory to write HDL files

• module_name (str) – Name of the top-level module

• format (str) – HDL format - “verilog” or “vhdl” (only verilog supported currently)

• pipeline_stages (int) – Number of pipeline stages (0 = combinational, see get_verilog_code)

Return type:

None

compile(opt_level=1, save_lib_path=None, verbose=False)

Compile the network to a shared library.

forward(x, verbose=False)

Forward pass through the compiled network.

Return type:

IntTensor

static load(save_lib_path, input_shape, num_classes=None, num_bits=64)

Load a compiled network from a shared library.

Note: input_shape is required here since we’re loading a pre-compiled library without access to the original model structure for inference.